题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output wire [7:0]d
);
wire [7:0] c1;
wire [7:0] c2;
mod mod_inst1
(
	 .clk(clk),
	 .rst_n(rst_n),
	 .a(a),
	 .b(b),
	 .c(c1)
);
mod mod_inst2
(
	 .clk(clk),
	 .rst_n(rst_n),
	 .a(a),
	 .b(c),
	 .c(c2)
);
mod mod_inst3
(
	 .clk(clk),
	 .rst_n(rst_n),
	 .a(c1),
	 .b(c2),
	 .c(d)
);
endmodule

module mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	output reg [7:0]c
);
always @(posedge clk or negedge rst_n)
 if (rst_n == 1'b0)
   c <= 8'b0;
 else if (a >= b)
   c <= b;
 else
   c <= a;
endmodule