题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);
parameter  data_reg=6'b001011;
reg [2:0] cnt;
always @(posedge clk or negedge rst_n)
if(!rst_n)
cnt<=3'd0;
else
cnt<=(cnt == 3'd5) ? 0:cnt+1;

always @ (posedge clk or posedge rst_n)
if(!rst_n)
data<=1'b0;
else
data<=data_reg[5-cnt];

endmodule