题解 | #数据累加输出#

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);

reg	[2:0]	r_cnt;

assign	ready_a = (r_cnt == 3'd4) ? ready_b : 1'b1;

always@(posedge clk or negedge rst_n)
	if (!rst_n)
		r_cnt <= 1'b0;
	else if (valid_a) begin
		if (r_cnt == 3'd4)
			r_cnt <= ready_b ? 1'b1 : r_cnt;
		else
			r_cnt <= r_cnt + 1'b1;
	end
	else
		r_cnt <= r_cnt;

always@(posedge clk or negedge rst_n)
	if (!rst_n)
		data_out <= 9'b0;
	else if (valid_a) begin
		if (r_cnt != 3'd4)
			data_out <= data_out + data_in;
		else if (ready_b)
			data_out <= data_in;
		else
			data_out <= data_out;	
	end
	else
		data_out <= data_out;		

always@(*)
	if (!rst_n)
		valid_b = 1'b0;
	else
		valid_b = (r_cnt == 3'd4) ? 1'b1 : 1'b0;

endmodule