题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

parameter	[2:0]	IDLE = 3'd0,
					GET_0 = 3'd1,
					GET_01 = 3'd2,
					GET_011 = 3'd3,
					GET_0111 = 3'd4,
					GET_01110 = 3'd5,
					GET_011100 = 3'd6,
					NO_MATCH = 3'd7;

reg		[2:0]	c_state,n_state,cnt;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		cnt <= 3'b0;
	else if(cnt == 3'd6)
		cnt <= 3'b1;
	else
		cnt <= cnt + 1'b1;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		c_state <= IDLE;
	else
		c_state <= n_state;

always@(*)
	case(c_state)
	IDLE		:	n_state = data ? NO_MATCH 	: GET_0		;
	GET_0		:	n_state = data ? GET_01 	: NO_MATCH	;
	GET_01		:	n_state = data ? GET_011 	: NO_MATCH	;
	GET_011		:	n_state = data ? GET_0111 	: NO_MATCH	;
	GET_0111	:	n_state = data ? NO_MATCH	: GET_01110 ;
	GET_01110	:	n_state = data ? NO_MATCH 	: GET_011100;
	GET_011100	:	n_state = data ? NO_MATCH 	: GET_0		;
	NO_MATCH	:	n_state = (~|cnt) ? (data ? NO_MATCH : GET_0) : NO_MATCH	;
	endcase

always@(*)
	if(!rst_n)
		match <= 1'b0;
	else if(c_state == GET_011100)
		match <= 1'b1;
	else
		match <= 1'b0;

always@(*)
	if(!rst_n)
		not_match <= 1'b0;
	else if((cnt == 3'd6)&(c_state == NO_MATCH))
		not_match <= 1'b1;
	else
		not_match <= 1'b0;

endmodule