题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);

reg		a_reg;

always@(posedge clk or negedge rst_n)
	if(~rst_n)
		a_reg <= 1'b0;
	else
		a_reg <= a;

always@(posedge clk or negedge rst_n)
	if(~rst_n)
		rise <= 1'b0;
	else if(!a_reg & a)
		rise <= 1'b1;
	else
		rise <= 1'b0;

always@(posedge clk or negedge rst_n)
	if(~rst_n)
		down <= 1'b0;
	else if(a_reg & ~a)
		down <= 1'b1;
	else
		down <= 1'b0;


endmodule