题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

  reg[7:0]check;
  wire match_w;
always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	check <= 8'b1111_1111;
	else
	check <= {check[6:0],a};
end
assign match_w = (check == 8'b01110001)?1:0;

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	match <= 1'b0;
	else
	match <= match_w;
end

endmodule