题解 | #对信号按位操作#
`timescale 1ns / 1ns module top_module ( input [4:0] in, output out_and, output out_or, output out_xor ); assign out_and = &in assign out_or = |in; assign out_xor = ^in; endmodule
`timescale 1ns / 1ns module top_module ( input [4:0] in, output out_and, output out_or, output out_xor ); assign out_and = &in assign out_or = |in; assign out_xor = ^in; endmodule
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