题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

	reg [2:0]	cnt;
	reg [5:0]	data_a_reg;

	always@(posedge clk or negedge rst_n)
		begin
			if(!rst_n)
				cnt <= 3'd0;
			else if(ready_a && valid_a)
				if(cnt == 3'd5)
					cnt <= 3'd0;
				else
					cnt <= cnt + 1'b1;
		end

	always@(posedge clk or negedge rst_n)
		begin
			if(!rst_n)
				ready_a <= 1'b0;
			else
				ready_a <= 1'b1;
		end

	always@(posedge clk or negedge rst_n)
		begin
			if(!rst_n)
				valid_b <= 1'b0;
			else if(cnt == 3'd5)
				valid_b <= 1'b1;
			else
				valid_b <= 1'b0;
		end

	always@(posedge clk or negedge rst_n)
		begin
			if(!rst_n)
				data_a_reg <= 6'b0;
			else if(ready_a && valid_a)
				data_a_reg <= {data_a,data_a_reg[5:1]};
		end

	always@(posedge clk or negedge rst_n)
		begin
			if(!rst_n)
				data_b <= 6'b0;
			else if(cnt == 3'd5)
				data_b <= {data_a,data_a_reg[5:1]};
		end
endmodule