题解 | #非整数倍数据位宽转换8to12#

得注意一下这个缓存数据，不然很容易出错

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);
//8*3=12*2
	reg[7:0] seq;
	reg [1:0] cnt;//0-2

	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			cnt<=0;
		else if(valid_in)begin
			if(cnt == 2'd2)
				cnt<=0;
			else
				cnt<=cnt+1;
		end
		else
			cnt<=cnt;
	
	// always@(posedge clk or negedge rst_n)
	// 	if(!rst_n)
	// 		seq<=0;
	// 	else if(valid_in)
	// 		seq<=data_in;
	// 	else
	// 		seq<=seq;
	
	// always@(posedge clk or negedge rst_n)
	// 	if(!rst_n)
	// 		data_out<=0;
	// 	else if(valid_in && cnt ==2'd1)
	// 		data_out<={seq,data_in[7:4]};
	// 	else if(valid_in && cnt ==2'd2)begin
	// 		data_out<={seq[7:4],data_in};
			
	// 	end
	// 	else
	// 		data_out<= data_out;
	
	always@(negedge rst_n or posedge clk)begin
        if(~rst_n)begin
            seq <= 0;
            data_out <= 0;
        end
        else if(valid_in)begin
            if(cnt == 1)begin
                data_out <= {seq, data_in[7:4]};
                seq <= data_in;
            end
            else if(cnt == 2)begin
                data_out <= {seq[3:0], data_in};
            end
            else
                seq <= data_in;
            end
    end

	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			valid_out<=0;
		else if(valid_in && (cnt ==2'd1 || cnt ==2'd2))
			valid_out<=1;
		else
			valid_out<=0;

endmodule