题解 | #信号反转输出#

`timescale 1ns/1ns

module top_module(
    input [15:0] in,
	output [15:0] out
);
    genvar i;
    generate    
        for(i=0;i<=15;i=i+1)
        begin
            assign out[15-i] = in[i];
        end     
    endgenerate
endmodule