题解 | #信号反转输出#

`timescale 1ns/1ns

module top_module(
    input [15:0] in,
	output [15:0] out
);
    reg [15:0] out1;
    integer i;
    always @*
    begin
        for (i=0;i<=15;i=i+1)
            begin 
                out1[15-i]=in[i];
            end     
    end
    assign out=out1;
endmodule