题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

reg	[2:0]	data_reg;

 always@(posedge clk or negedge rst_n)
	if(!rst_n)
		data_reg	<=	4'd0;
	else	if(data_valid)	
		data_reg	<={data_reg[2:0],data};
	else	
		data_reg	<=	data_reg;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		match	<=	1'b0;

	else	if(data_reg	== 3'b011 && !data)
		match	<=	1'b1;
	else
		match	<=	1'b0;	


endmodule