题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);

	reg data_Q0;
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data_Q0 <= 0;
		end
		else begin
			data_Q0 <= data_in;
		end
	end

	/*always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data_out <= 0;
		end
		else begin
			data_out <= (~data_Q0) & data_in;
		end
	end*/

	reg data_D1;
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			data_D1 <= 0;
		end
		else begin
			data_D1 <= (~data_Q0) & data_in;
		end
	end

	always @(*) begin
		if(!rst_n) begin
			data_out <= 0;
		end
		else begin
			data_out <= data_D1;
		end
	end

endmodule