题解 | #格雷码计数器#

`timescale 1ns/1ns

module gray_counter(
   input   clk,
   input   rst_n,

   output  reg [3:0] gray_out
);

//格雷码是一种相邻数据只有1bit变化的码制
//计数器两个周期+1  ————即需要一个二分频
//1、格雷码转二进制 2、加法器 3、二进制转格雷码

//两个周期
reg clk_2;
always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        clk_2 <= 0;
    end
    else begin
        clk_2 <= ~clk_2;
    end
end

//两个周期计数器加1
reg [3:0] counter;
always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        counter <= 0;
    end
    else begin
        counter <= clk_2? counter + 1 : counter;
    end
end


always @(*) begin
    if(!rst_n) begin
        gray_out <= 0;
    end
    else begin
        gray_out <= counter ^ (counter >> 1);
    end
end







endmodule