题解 | #信号发生器#

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [4:0]wave
	);
reg flag = 1'b1;
reg[4:0] cnt = 5'b00000;
always@(posedge clk or negedge rst_n)
	if(~rst_n)
		wave <= 5'b00000;
	else
		case(wave_choise)
		0:
			begin
				if(cnt == 5'b10011)
					cnt <= 5'b00000;
				else
					cnt <= cnt + 1;
				begin			
				wave <= (cnt == 5'b01001)? 5'b10100:
						(cnt == 5'b10011)? 5'b00000:
						wave; 
				flag <= 1'b1;
				end
			end
		1:
			begin
				wave <= (wave==20)? 0 : wave+1;
				flag <= 1'b1;
			end
		2:
			begin
				if(((wave==5'b10011)&&(flag==1'b0)))
					flag <= 1'b1;
				if(((wave==5'b00001)&&(flag==1'b1)))
					flag <= 1'b0;
				begin
				wave <= flag? wave-1 : wave+1;
				end
			end
		endcase
  
endmodule