题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
    reg clk2,clk4,clk8;
    always @(posedge clk_in or negedge rst) begin
        if(!rst)
            clk2 <= 0;
        else
            clk2 <= ~clk2;
    end
    assign clk_out2 = clk2;
    always @(posedge clk2 or negedge rst) begin
        if(!rst)
            clk4 <= 0;
        else
            clk4 <= ~clk4;
    end
    assign clk_out4 = clk4;
    always @(posedge clk4 or negedge rst) begin
        if(!rst)
            clk8 <= 0;
        else
            clk8 <= ~clk8;
    end
    assign clk_out8 = clk8;


//*************code***********//
endmodule