题解 | #ROM的简单实现#
ROM的简单实现
https://www.nowcoder.com/practice/b76fdef7ffa747909b0ea46e0d13738a
`timescale 1ns/1ns
module rom(
input clk,
input rst_n,
input [7:0]addr,
output wire [3:0]data
);
reg [3:0] reg_rom[7:0];
reg [3:0] data_reg ;
integer i = 0;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
for( i = 0; i <=7 ; i = i + 1)
begin
reg_rom[i] <= i*2;
end
end
end
always@(*)begin
if(!rst_n)
data_reg = 4'd0;
else begin
data_reg = reg_rom[addr];
end
end
assign data = data_reg;
endmodule
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