题解 | #自动贩售机2#

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//

reg [6:0]state;
parameter s0 = 7'b000_0001;
parameter s1 = 7'b000_0010;
parameter s2 = 7'b000_0100;
parameter s3 = 7'b000_1000;
parameter s4 = 7'b001_0000;
parameter s5 = 7'b010_0000;
parameter s6 = 7'b100_0000;

always@(posedge clk or negedge rst)
    if (rst == 1'b0)
	    state <= s0;
	else if (sel == 1'b0) 
	    case(state)
		    s0 : 
			    if (d1 == 1'b1)
				    state <= s1;
				else if (d2 == 1'b1)
				    state <= s2;
				else 
				    state <= s0;
			s1 : 
			    if (d1 == 1'b1)
				    state <= s2;
				else if (d2 == 1'b1)
				    state <= s3;
				else 
				    state <= s1;
			s2 : 
			    if (d1 == 1'b1)
				    state <= s3;
				else if (d2 == 1'b1)
				    state <= s4;
				else 
				    state <= s2;
			s3 : 
			    state <= s0;
			s4 : 
			    state <= s0;
			default : state <= s0;
		endcase
			

always@(posedge clk or negedge rst)
    if (rst == 1'b0)
	    state <= s0;
	else if (sel == 1'b1) 
	    case(state)
		    s0 : 
			    if (d1 == 1'b1)
				    state <= s1;
				else if (d2 == 1'b1)
				    state <= s2;
				else 
				    state <= s0;
			s1 : 
			    if (d1 == 1'b1)
				    state <= s2;
				else if (d2 == 1'b1)
				    state <= s3;
				else 
				    state <= s1;
			s2 : 
			    if (d1 == 1'b1)
				    state <= s3;
				else if (d2 == 1'b1)
				    state <= s4;
				else 
				    state <= s2;
			s3 : 
			    if (d1 == 1'b1)
				    state <= s4;
				else if (d2 == 1'b1)
				    state <= s5;
				else 
				    state <= s3;
			s4 : 
			    if (d1 == 1'b1)
				    state <= s5;
				else if (d2 == 1'b1)
				    state <= s6;
				else 
				    state <= s4;
			s5 : 
				state <= s0;
			s6 : 
				state <= s0;
			default : state <= s0;
		endcase

always@(posedge clk or negedge rst)
    if (rst == 1'b0)
	    begin
	        out1 <= 1'b0;
			out2 <= 1'b0;
			out3 <= 1'b0;
		end
	else if (state == s3 && sel == 1'b0)
	     begin
	        out1 <= 1'b1;
			out2 <= 1'b0;
			out3 <= 1'b0;
		end
	else if (state == s4 && sel == 1'b0)
	     begin
	        out1 <= 1'b1;
			out2 <= 1'b0;
			out3 <= 1'b1;
		end
	else if (state == s5 && sel == 1'b1)
	     begin
	        out1 <= 1'b0;
			out2 <= 1'b1;
			out3 <= 1'b0;
		end
	else if (state == s6 && sel == 1'b1)
	     begin
	        out1 <= 1'b0;
			out2 <= 1'b1;
			out3 <= 1'b1;
		end
	else 
	    begin
			out1 <= 1'b0;
			out2 <= 1'b0;
			out3 <= 1'b0;
		end


//*************code***********//
endmodule

用了两个状态机，第一个状态机是在sel 1'b0 时执行的状态机，对应饮料1的输出；第二个状态机是在sel == 1'b1时执行的，对应饮料2的输出。（采用二段式状态机写法）