题解 | #加减计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input mode,
	output reg [3:0]number,
	output reg zero
	);
	reg			[3:0]		cnt ;
	always @(posedge clk or negedge rst_n ) begin
		if(!rst_n) begin
			cnt <= 4'b0 ;
		end
		else if(cnt == 4'b0 && !mode) begin
			cnt <= 4'd9 ;
		end
		else if(cnt == 4'd9 && mode) begin
			cnt <= 4'b0 ;
		end
		else if(mode) begin
			cnt <= cnt + 4'b1 ;
		end
		else begin
			cnt <= cnt - 4'b1 ;
		end
	end
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			zero <=1'b0 ;
		end
		else if(cnt == 1'b0 )begin
			zero <=1'b1 ;
		end
		else begin
			zero <=1'b0 ;
		end
	end
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			number <=1'b0 ;
		end
		else begin
			number <=cnt ;
		end
	end
endmodule