题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
	
	reg [1:0] a_reg;
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			a_reg[0] <= 0;
			a_reg[1] <= 0;
		end
		else begin
			a_reg[1] <= a;
			a_reg[0] <= a_reg[1];
		end
	end

	//assign rise = (a_reg == 2'b01);
	//assign down = (a_reg == 2'b10);

	always @(*) begin
		if(!rst_n) begin
			rise <= 0;
			down <= 0;
		end
		else if(a_reg == 2'b10) begin//a_reg[1] = 1;a_reg[0] = 0 即先是低电平 后高电平————上升沿（边沿检测最好直接判断先后顺序，画波形图容易搞混）
			rise <= 1;
			down <= 0;
		end
		else if(a_reg == 2'b01) begin//a_reg[1] = 0;a_reg[0] = 1 即先是高电平 后低电平————下升沿
			rise <= 0;
			down <= 1;
		end
		else begin
			rise <= 0;
			down <= 0;
		end
	end


endmodule