题解 | #ROM的简单实现#

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);
	/*parameter pre_data = 32'hECA86420;
	//parameter pre_data = 32'h02468ACE;

	reg data;
	always @(*) begin
		if(!rst_n) begin
			data <= 0;
		end
		else begin
			case(addr) 
				0: data <= pre_data[3:0];
				1: data <= pre_data[7:4];
				2: data <= pre_data[11:8];
				3: data <= pre_data[15:12];
				4: data <= pre_data[19:16];
				5: data <= pre_data[23:20];
				6: data <= pre_data[27:24];
				7: data <= pre_data[31:28];
				default: data <= 0;
			endcase
		end
	end
	*/

	//声明存储器空间
	reg [3:0] rom_data[7:0];//[地址位长] rom_data [数据位长]
	//初始化rom_data数据
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			rom_data[0] <= 4'd0;
			rom_data[1] <= 4'd2;
			rom_data[2] <= 4'd4;
			rom_data[3] <= 4'd6;
			rom_data[4] <= 4'd8;
			rom_data[5] <= 4'd10;
			rom_data[6] <= 4'd12;
			rom_data[7] <= 4'd14;
		end
		else begin
			rom_data[0] <= rom_data[0];
			rom_data[1] <= rom_data[1];
			rom_data[2] <= rom_data[2];
			rom_data[3] <= rom_data[3];
			rom_data[4] <= rom_data[4];
			rom_data[5] <= rom_data[5];
			rom_data[6] <= rom_data[6];
			rom_data[7] <= rom_data[7];
		end
	end

	assign data = rom_data[addr];






endmodule