题解 | #ROM的简单实现#

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);
	parameter pre_data = 32'hECA86420;
	//parameter pre_data = 32'h02468ACE;

	reg data;
	always @(*) begin
		if(!rst_n) begin
			data <= 0;
		end
		else begin
			case(addr) 
				0: data <= pre_data[3:0];
				1: data <= pre_data[7:4];
				2: data <= pre_data[11:8];
				3: data <= pre_data[15:12];
				4: data <= pre_data[19:16];
				5: data <= pre_data[23:20];
				6: data <= pre_data[27:24];
				7: data <= pre_data[31:28];
				default: data <= 0;
			endcase
		end
	end




endmodule