题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);

    parameter st_00 = 2'b00;
    parameter st_01 = 2'b01;
    parameter st_10 = 2'b10;
    parameter st_11 = 2'b11;

    reg [1:0] st_cur;
    reg [1:0] st_next;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            st_cur <= 2'b00;
            st_next <= 2'b00;
        end
        else begin
            st_cur <= st_next;
        end
    end
    reg Y0;
    always @(*) begin
        case(C)
            0:
                case(st_cur)
                    2'b00: begin st_next <= st_00; Y0 <= 0; end
                    2'b01: begin st_next <= st_11; Y0 <= 0; end
                    2'b10: begin st_next <= st_00; Y0 <= 0; end
                    2'b11: begin st_next <= st_11; Y0 <= 1; end
                endcase
            1:
                case(st_cur)
                    2'b00: begin st_next <= st_01; Y0 <= 0; end
                    2'b01: begin st_next <= st_01; Y0 <= 0; end
                    2'b10: begin st_next <= st_10; Y0 <= 1; end
                    2'b11: begin st_next <= st_10; Y0 <= 1; end
                endcase
        endcase
    end

    assign Y = Y0;

                    
endmodule