题解 | #ROM的简单实现#

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);
	reg		[3:0]	ram [0:7] ;
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			ram[0] <= 4'b0 ;
			ram[1] <= 4'd2 ;
			ram[2] <= 4'd4 ;
			ram[3] <= 4'd6 ;
			ram[4] <= 4'd8 ;
			ram[5] <= 4'd10 ;
			ram[6] <= 4'd12 ;
			ram[7] <= 4'd14 ;
		end
		else begin
			ram[0] <= 4'b0 ;
			ram[1] <= 4'd2 ;
			ram[2] <= 4'd4 ;
			ram[3] <= 4'd6 ;
			ram[4] <= 4'd8 ;
			ram[5] <= 4'd10 ;
			ram[6] <= 4'd12 ;
			ram[7] <= 4'd14 ;		end
	end
	assign data = ram[addr] ;
endmodule