题解 | #信号级联合并#

`timescale 1ns/1ns

module top_module(
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );

    wire [31:0] temp;
    assign temp = {a,b,c,d,e,f,2'b11};
    assign {w,x,y,z} = {temp[31:24],temp[23:16],temp[15:8],temp[7:0]};
endmodule