题解 | #使用generate…for语句简化代码#

`timescale 1ns/1ns
module gen_for_module( 
    input [7:0] data_in,
    output [7:0] data_out
);
    genvar      cnt ;
    generate 
        for(cnt = 0 ; cnt <8 ; cnt = cnt +1)
            begin : reverse_data
                assign data_out[cnt] = data_in[7-cnt] ;
            end
    endgenerate

endmodule