题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//
reg     [15:0]      data_lock ;
always @(posedge clk or negedge rst) begin
    if(!rst) begin
        data_lock <= 16'b0 ;
    end
    else if(!sel) begin
        data_lock <= d ;
    end
    else begin
        data_lock <= data_lock ;
    end
end
always @(posedge clk or negedge rst) begin
    if(!rst) begin
        out <= 5'b0 ;
    end
    else begin
        case(sel)
            2'd0: begin
                out <= 5'b0 ;
            end
            2'd1: begin
                out <= data_lock[3:0] + data_lock[7:4]  ;
            end
            2'd2: begin
                out <= data_lock[3:0] + data_lock[11:8] ;
            end
            2'd3: begin
                out <= data_lock[3:0] + data_lock[15:12];
            end
        default : begin
               out <= data_lock[3:0] + data_lock[15:12];
        end
        endcase
    end
end
always @(posedge clk or negedge rst) begin
    if(!rst) begin
        validout <= 1'b0 ;
    end
    else if(sel != 2'd0)
        validout <= 1'b1 ;
    else 
        validout <= 1'b0 ;
end
//*************code***********//
endmodule