题解 | #ROM的简单实现#

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);
reg  [3:0]data;
reg [3:0]buff[7:0];
always@(posedge clk or negedge rst_n)
   begin if(!rst_n)
         begin buff[0]<=0;
		       buff[1]<=2;
			   buff[2]<=4;
			   buff[3]<=6;
			   buff[4]<=8;
			   buff[5]<=10;
			   buff[6]<=12;
			   buff[7]<=14;
		 end
   end
   always@(*)
   begin if(!rst_n)
   data=0;
   else data=buff[addr];
   end
endmodule