题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//

parameter S0=5'b000_01;
parameter S1=5'b000_10;
parameter S2=5'b001_00;
parameter S3=5'b010_00;
parameter S4=5'b100_00;

reg [4:0] cur_state,next_state;

always@(posedge clk or negedge rst)begin
	if(!rst)
		cur_state <= S0;
	else
		cur_state <= next_state;
end


//*************code***********//
always@(*)begin
	if(!rst)
		next_state = S0;
	else
		case(cur_state)
				S0	   : next_state = data? S1: S0;
                S1     : next_state = data? S1: S2;
                S2     : next_state = data? S3: S0;
                S3     : next_state = data? S4: S2;
                S4     : next_state = data? S1: S2;
                default: next_state = S0;
	endcase
end

always@(posedge clk or negedge rst)begin
	if(!rst)
		flag <= 0;
	else if(cur_state==S4)  //与上一题的区别在于，本题flag输出之后当前状态，所以用当前状态判断
		flag <= 1;
	else
		flag <= 0;
end


//*************code***********//
endmodule