题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

//*************code***********//
parameter s0=0;
parameter s1=1;
parameter s2=2;
parameter s3=3;
parameter s4=4;
reg[2:0]state;
reg[2:0]next_state;
//1
always@(posedge clk or negedge rst)
begin 
	if(!rst)
	state<=0;
	else state<=next_state;
end
//2

always@(*)
begin
	if(!rst)
	begin next_state=0;
	flag=0; 
	end 
	else 
	begin case(state)
	s0:if(data==1) begin next_state=s1; flag=0;end  else begin next_state=s0;flag=0;end 
	s1:if(data==1) begin next_state=s2; flag=0;end else begin next_state=s1;flag=0;end 
	s2:if(data==1)  begin next_state=s3; flag=0;end else begin next_state=s2;flag=0;end 
	s3:if(data==1) begin next_state=s4;flag=0;end  else begin next_state=s3;flag=0;end 
	s4:if(data==1) begin  next_state=s1; flag=1;end  else begin next_state=s0;flag=1;end 
	default:begin next_state=s0; flag=0;end 
	endcase
	end
end

//*************code***********//
endmodule