题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
	reg a_before,a_now;

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
		begin
			a_before <= 1'b0;
			a_now <= 1'b0;
		end
		else 
			begin
			a_before <= a_now;
			a_now <= a;
			end
	end

	always@(*)begin
		if(!rst_n)
		begin
			rise <= 1'b0;
			down <= 1'b0;
		end
		else 
			case({a_before,a_now})
				2'b00:begin
					rise <=1'b0;
					down <=1'b0;
				end
				2'b01:begin
					rise <=1'b1;
					down <=1'b0;
				end
				2'b10:begin
					rise <=1'b0;
					down <=1'b1;
				end
				2'b11:begin
					rise <=1'b0;
					down <=1'b0;
				end
			endcase
	end
	
endmodule