题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
reg [5:0] data_b_ray;
reg [2:0] data_num;
always @(posedge clk or negedge rst_n) begin
	if (~rst_n) begin
		data_b_ray <= 0;
		data_num <= 0;
		ready_a <= 0;
		valid_b <= 0;
		data_b <= 0;
	end
	else begin
		ready_a <= 1;
		if (valid_a) begin
			data_b_ray <= {data_a,data_b_ray[5:1]};
			if (data_num<5)
				data_num <= data_num + 1;
			else
				data_num <= 0;
		end
		if (data_num==5 && valid_a == 1 ) begin
			valid_b <= 1;
			data_b <=  {data_a,data_b_ray[5:1]};
		end
		else
			valid_b <= 0;
	end
end
endmodule

为了使valid_b只有一个时钟周期为1，判断：已输入5位有效数据并且该时钟周期中valid_a为1，即下个时钟周期输入6位有效数据。