题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
    reg data_tmp;

    always @ (posedge clk, negedge rst) begin
        if (!rst) begin
            data_tmp <= 1'b0;
        end
        else if (data == 1'b1) begin
            data_tmp <= !data_tmp;
        end
    end

    always @ (posedge clk, rst) begin
        if (!rst) begin
            q <= 1'b0;
        end
        else if (data_tmp == 1'b1) begin
            q <= !q;
        end
    end

//*************code***********//
endmodule