题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

	reg [2:0]     cnt     ;
	wire          add_cnt ;
	wire          end_cnt ;

	reg [5:0]     temp_b  ;

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			ready_a <= 1'b0;
		end
		else begin
			ready_a <= 1'b1;
		end
	end

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			cnt <= 1'b0;
		end	
		else if(add_cnt)begin
			if(end_cnt)begin
				cnt <= 1'b0;
			end
			else begin
				cnt <= cnt + 1;
			end
		end
	end
	assign add_cnt = ready_a && valid_a;
	assign end_cnt = add_cnt && cnt == 6 -1;

	always@(posedge clk or negedge rst_n)begin
        if(!rst_n) 
			temp_b <= 'd0;
        else if(ready_a && valid_a) 
			temp_b <= {data_a, temp_b[5 : 1]};
    end

	always@(posedge clk or negedge rst_n)begin
        if(!rst_n) 
			valid_b <= 'd0;
        else if(end_cnt) 
			valid_b <= 1'b1;
        else 
			valid_b <= 1'b0;
    end

	always@(posedge clk or negedge rst_n)begin
        if(!rst_n) 
			data_b <= 'd0;
        else if(end_cnt) 
			data_b <= {data_a, temp_b[5 : 1]};
    end

endmodule