题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg 	[3:0]	state,next_state;
localparam	BIT1 = 4'b0000,	/*8'b0000_0000,*/
			BIT2 = 4'b0001,	/*8'b0000_0001,*/
			BIT3 = 4'b0010,	/*8'b0000_0011,*/
			BIT4 = 4'b0011,	/*8'b0000_0111,*/
			BIT5 = 4'b0100,	/*8'b0000_1110,*/
			BIT6 = 4'b0101,	/*8'b0001_1100,*/
			BIT7 = 4'b0110,	/*8'b0011_1000,*/
			BIT8 = 4'b0111,	/*8'b0111_0001;*/
			BIT0 = 4'b1000;

always @(posedge clk or rst_n)begin
	if(!rst_n)begin
		state	<= 3'b0;
	end
	else begin
		state	<= next_state;
	end
end

always @(*)begin
	case(state)
		BIT0: begin next_state = (a==0)? BIT1 : BIT0;	end
		BIT1: begin next_state = (a==1)? BIT2 : BIT1;	end
		BIT2: begin next_state = (a==1)? BIT3 : BIT1;	end
		BIT3: begin next_state = (a==1)? BIT4 : BIT1;	end
		BIT4: begin next_state = (a==0)? BIT5 : BIT0;	end
		BIT5: begin next_state = (a==0)? BIT6 :	BIT2;	end
		BIT6: begin next_state = (a==0)? BIT7 : BIT2;	end
		BIT7: begin next_state = (a==1)? BIT8 : BIT1;	end
		BIT8: begin next_state = (a==1)? BIT3 : BIT1;	end
	endcase
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n)
		match <= 1'b0;
	else if(state == BIT8)
		match <= 1'b1;
	else
		match <= 1'b0;
end  
endmodule

使用状态机进行序列检测。