题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
reg ar ;
always @(posedge clk or negedge rst_n)
	if(!rst_n)
		ar <= 0 ;
	else
		ar <= a ;

always @(posedge clk or negedge rst_n)
	if(!rst_n)
		rise <= 0;
	else if (a && ~ar)
		rise <= 1;
	else if (rise)
		rise <= 0;

always @(posedge clk or negedge rst_n)
	if(!rst_n)
		down <= 0;
	else if (~a && ar)
		down <= 1;
	else if (down)
		down <= 0;

endmodule

边沿检测 将原信号打一拍再进行对比 画出波形图一目了然