题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4,s5=3'd5,s6=3'd6,s7=3'd7;
reg [2:0] state, next;

always @ (posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		state<=s0;
	end
	else begin
		state<=next;
	end
end


always @ (*) begin
	case(state)
	s0:next=(~data&data_valid)?s1:s0;
	s1:next=(data&data_valid)?s2:(~data&data_valid)?s1:s1;
	s2:next=(data&data_valid)?s3:(~data&data_valid)?s1:s2;
	s3:next=(~data&data_valid)?s1:(data&data_valid)?s0:s3;
	endcase
end


always @(posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		match<=1'd0;
	end
	else begin
		if(state==s3 & data_valid & ~data) begin
			match<=1'd1;
		end
		else begin
			match<=1'd0;
		end
	end
end


  
endmodule