题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
wire [7:0]min_ab;
wire [7:0]min_ac;
wire [7:0]min_abc;
sub_mod sub_mod0(
	.clk(clk),
	.rst_n(rst_n),
	.a(a),
	.b(b),
	.c(min_ab)
);
sub_mod sub_mod1(
	.clk(clk),
	.rst_n(rst_n),
	.a(a),
	.b(c),
	.c(min_ac)
);
sub_mod sub_mod2(
	.clk(clk),
	.rst_n(rst_n),
	.a(min_ab),
	.b(min_ac),
	.c(min_abc)
);
assign d=min_abc;
endmodule
module sub_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	output [7:0]c
);
reg[7:0]c;
always@(posedge clk or negedge rst_n)
if(~rst_n)begin
	c<=8'b0;
end
else begin
	c<=a<b?a:b;
end
endmodule