题解 | #自动贩售机2#

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
//这题和上题类似，不过多一个判断




reg [2:0] d;



always @(posedge clk or negedge rst)begin
	if(~rst)
	d <= 3'b0;
	else if((d < 3'd3)&&(sel == 0))
	d <= d + {d2,d1};
	else if((d < 3'd5)&&(sel == 1))
	d <= d + {d2,d1};
	else
	d <= 3'b0;

end


always @(posedge clk or negedge rst)begin
	if(~rst) begin
	out1 <= 1'b0;
	out2 <= 1'b0;
	end
	else if((d > 3'd2)&&(sel == 0))
	out1 <= 1'b1;
	else if((d > 3'd4)&&(sel == 1))
	out2 <= 1'b1;
	else begin
	out1 <= 1'b0;
	out2 <= 1'b0;
	end

end


always @(posedge clk or negedge rst)begin
	if(~rst)
	out3 <= 1'b0;
	else if((d > 3'd2)&&(sel == 0))
	out3 <= d-3'd3;
	else if((d > 3'd4)&&(sel == 1))
	out3 <= d-3'd5;
	else
	out3 <= 3'b0;
end



//*************code***********//
endmodule