题解 | #任意小数分频#

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//*************code***********//
reg [7:0] count;
reg [4:0] count_e, count_o;
always@(posedge clk_in or negedge rst) begin
    if(~rst) begin
        count <= 0;
        count_e <= 0;
        count_o <= 0;
    end
    else begin
        count <= (count == M_N-1)? 0 : count+1;
        count_e <= ((count >= c89) || count_e==div_e-1)? 0 : count_e+1;
        count_o <= ((count < c89) || count_o==div_o-1)? 0 : count_o+1;
    end
end
reg clk_div_8,clk_div_9;
always@(posedge clk_in or negedge rst) begin
    if(~rst) clk_div_8 <= 0;
    //else clk_div_8 <= ((count < c89) && (count_e==5'd0 || count_e==5'd4))? ~clk_div_8 : clk_div_8;
    else clk_div_8 <= ((count < c89) && (count_e < 5'd4));

end
always@(posedge clk_in or negedge rst) begin
    if(~rst) clk_div_9 <= 0;
    // else clk_div_9 <= ((count >= c89) && (count_o==5'd0 || count_o==5'd4))? ~clk_div_9 : clk_div_9;
    else clk_div_9 <= ((count >= c89) && (count_o < 5'd4));

end
assign clk_out = (count < c89)? clk_div_8 : clk_div_9;
//*************code***********//
endmodule