题解 | #自动贩售机1#

`timescale 1ns/1ns
module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//
reg [2:0] money;
always@(posedge clk or negedge rst) begin
	if(!rst) money <= 0;
	else money <= (money>=3'd3)? 0 : money + {d3,d2,d1};
end
always@(posedge clk or negedge rst) begin
	if(!rst) begin
		out1 <= 0;
		out2 <= 0;
	end
	else case(money)
		3'b011: begin 
			out1 <= 1;
			out2 <= 0;
		end
		3'b100: begin 
			out1 <= 1;
			out2 <= 1;
		end
		3'b101: begin 
			out1 <= 1;
			out2 <= 2;
		end
		3'b110: begin 
			out1 <= 1;
			out2 <= 3;
		end
		default: begin
			out1 <= 0;
			out2 <= 0;
		end
		endcase
end
//*************code***********//
endmodule