题解 | #移位运算与乘法#

标准三段式状态机

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);

reg [1:0]state;
reg [1:0]next_state;
reg [7:0]din;

always@(posedge clk or negedge rst) begin
    if(~rst)
        state<=2'b00;
    else 
        state <= next_state;
end

always@(*)begin
    next_state <= state + 2'b01;
end

always @(posedge clk or negedge rst) begin
    if(~rst)
        out <= 'b0;
    else begin
        case(state)
            2'b00:out <=d;
            2'b01:out <=(din<<1)+din;
            2'b10:out <=(din<<3)-din;
            2'b11:out <=(din<<3);
        endcase
    end
end
    
always @(posedge clk or negedge rst) begin
    if(~rst)
        begin
            input_grant <= 1'b0;
            din <= 8'b0;
        end 
    else if(state == 2'b00)
        begin
            input_grant<=1'b1;
            din<=d; 
        end
    else
        input_grant<=1'b0;
end

endmodule