题解 | #状态机与时钟分频#

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

parameter s0=4'b1000;
parameter s1=4'b0100;
parameter s2=4'b0010;
parameter s3=4'b0001;
reg [3:0]state_c;
reg [3:0]state_n;
//状态转移
always@(posedge clk or negedge rst)begin
	if(!rst)
		state_c<=s0;
	else 
		state_c<=state_n;
end
//逻辑转移
always@(*)begin
	case(state_c)
		s0:state_n<=s1;
		s1:state_n<=s2;
		s2:state_n<=s3;
		s3:state_n<=s0;
		default:state_n<=s0;
	endcase
end
	
always@(posedge clk or negedge rst)begin
	if(!rst)
		clk_out<=0;
	else if(state_c==s0)
		clk_out<=1'd1;
	else
		clk_out<=0;
end


endmodule