题解 | #交通灯#

`timescale 1ns/1ns

module triffic_light(
    input rst_n,
    input clk,
    input pass_request,
    output wire [7:0] clock,
    output reg red,
    output reg yellow,
    output reg green
);

parameter IDEL=0, R=1, Y=2, G=3;

reg [1:0] cstate, nstate;
always@(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        cstate <= IDEL;
    end
    else begin
        cstate <= nstate;
    end
end

reg [5:0] cnt;
always@(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        cnt <= 'd0;
    end
    else begin
        if(cstate!=nstate) begin
            cnt <= 'd0;
        end
        else begin
            case(cstate)
                G: cnt <= pass_request?'d49:(cnt+'d1);
                Y,
                R: cnt <= cnt + 'd1;
                default: cnt <= 'd0;
            endcase
        end
    end
end

always@(*) begin
    case(cstate)
        IDEL: nstate = R;
        R: nstate = (cnt=='d9)?Y:cstate;
        Y: nstate = (cnt=='d4)?G:cstate;
        G: nstate = (cnt=='d59)?R:cstate;
        default: nstate = IDEL;
    endcase
end

always@(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        {green,yellow,red} <= 3'b000;
    end
    else begin
        case(cstate)
            G: {green,yellow,red} <= 3'b100;
            Y: {green,yellow,red} <= 3'b010;
            R: {green,yellow,red} <= 3'b001;
            default: {green,yellow,red} <= 3'b000;
        endcase
    end
end

reg [7:0] clock_reg;
always@(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        clock_reg <= 'd0;
    end
    else begin
        clock_reg <= (cstate==G)?('d60-cnt):((cstate==Y)?('d5-cnt):('d10-cnt));
    end
end

assign clock = clock_reg;

endmodule