题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

//*************code***********//
    localparam    S0 = 5'b0_0001;
    localparam    S1 = 5'b0_0010;
    localparam    S2 = 5'b0_0100;
    localparam    S3 = 5'b0_1000;
    localparam    S4 = 5'b1_0000;
    
    reg    [4:0]    cur_state;
    reg    [4:0]    nex_state;
    
    always@(posedge clk or negedge rst)
    begin
        if(!rst)
            cur_state <= S0;
        else
            cur_state <= nex_state;
    end
    
    always@(*)        //两段式状态机就是第二段的状态跳转以及输出是一起的，并且都是组合逻辑
    begin
        if(!rst)
            begin
                nex_state = S0;
                flag = 1'b0;
            end
        else
            begin
                case(cur_state)    //由状态转移图和波形图可以看到s4状态无论输入什么它都是直接跳转，只不过是跳转的状态不同而已，观察输出可知，其是在进入s4状态就输出1，和输入无关，并且是立马输出，之前的那个题是进入s3状态后要判断输入来进行输出，所以存在一个延时
                    S0    :    begin    //这个题中一进入s4状态就立马输出，也就是输出和输入无关，这个是一种状态机类型，其输出没有延时，所以在三段式状态机中也可以写，nex型对应s0和s1，其中s1需要判断当前状态，而cur型需要在s3时就判断，若是输入为1，则状态跳转，并且输出1，因为在s4状态时输出和输入无关，所以这个直接由状态来控制输出，就是说s4的状态控制输出
                            flag = 1'b0;
                            if(data)
                                nex_state = S1;
                            else
                                nex_state = S0;
                        end
                    S1    :    begin
                            flag = 1'b0;
                            if(data)
                                nex_state = S2;
                            else
                                nex_state = S1; 
                        end
                    S2    :    begin
                            flag = 1'b0;
                            if(data)
                                nex_state = S3;
                            else
                                nex_state = S2;
                        end
                    S3    :    begin
                            flag = 1'b0;
                            if(data)
                                nex_state = S4;
                            else
                                nex_state = S3;
                        end
                    S4    :    begin
                            if(data)
                                begin
                                    nex_state = S1;
                                    flag = 1'b1;
                                end
                            else
                                begin
                                    nex_state = S0;
                                    flag = 1'b1;
                                end
                        end
                    default    :    begin
                        nex_state = S0;
                        flag = 1'b0;
                    end
                endcase
            end
    end

//*************code***********//
endmodule