题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
    localparam    S0 = 4'b0001;
    localparam    S1 = 4'b0010;
    localparam    S2 = 4'b0100;
    localparam    S3 = 4'b1000;
    
    
    reg    [3:0]    cur_state;
    reg    [3:0]    nex_state;
    
    always@(posedge clk or negedge rst)
    begin
        if(!rst)
            cur_state <= S0;
        else
            cur_state <= nex_state;
    end
    
    always@(*)
    begin
        if(!rst)
            nex_state = S0;
        else
            begin
                case(cur_state)
                    S0    :    begin
                            if(data)
                                nex_state = S1;
                            else
                                nex_state = S0;
                        end
                    S1    :    begin
                            if(data)
                                nex_state = S2;
                            else
                                nex_state = S1;
                        end
                    S2    :    begin
                            if(data)
                                nex_state = S3;
                            else
                                nex_state = S2;
                        end
                    S3    :    begin
                            if(data)
                                nex_state = S0;
                            else
                                nex_state = S3;
                        end
                    default    :    nex_state = S0;
                endcase
            end
    end
    
    always@(posedge clk or negedge rst)
    begin
        if(!rst)
            flag <= 1'b0;
        else
            begin
                case(cur_state)
                    S0    :    begin
                        flag <= 1'b0;
                    end
                    S1    :    begin
                        flag <= 1'b0;
                    end
                    S2    :    begin
                        flag <= 1'b0;
                    end
                    S3    :    begin
                        if(data)            //这里需要引入判断，若是为0需要对其进行拉低，因为拉高的只需要一个时钟并且进行状态跳转
                            flag <= 1'b1;
                        else
                            flag <= 1'b0;
                    end
                    default    :    flag <= 1'b0;
                endcase
            end
    end
    

//*************code***********//
endmodule