题解 | #脉冲同步电路#
脉冲同步电路
https://www.nowcoder.com/practice/b7f37e6c55e24478aef4ec2d738bbf07
这次主要想练习握手法解法：
主要问题：
1、反压
2：注意请求信号fast_req，应答信号slow_ack的生成。
3：注意fast_ack，slow_req全部打三拍。
4：注意 assign dataout = (~slow_req[2]) & (slow_req[1]);进行上升沿检测。
`timescale 1ns/1ns
module pulse_detect(
input clk_fast ,
input clk_slow ,
input rst_n ,
input data_in ,
output dataout
);
reg fast_req, slow_ack;
reg [2:0] slow_req;
reg [2:0] fast_ack;
//fast时钟域
//将slow时钟域的应答信号打三拍，送到fast时钟域
always @(posedge clk_fast, negedge rst_n) begin
if(!rst_n) begin
fast_ack <= 3'b0;
end else begin
fast_ack <= {fast_ack[1:0], slow_ack};
end
end
//生成请求信号fast_req
always @(posedge clk_fast, negedge rst_n) begin
if(!rst_n) begin
fast_req <= 1'b0;
end else if (data_in) begin
fast_req <= 1'b1;
end else begin
fast_req <= (fast_ack[1] & (~fast_ack[2])) ? 1'b0 : fast_req;
end
end
//slow时钟域
//将fast时钟域的请求信号打三拍，送到slow时钟域
always @(posedge clk_slow, negedge rst_n) begin
if(!rst_n) begin
slow_req <= 3'b0;
end else begin
slow_req <= {slow_req[1:0], fast_req};
end
end
//生成应答信号slow_ack
always @(posedge clk_slow, negedge rst_n) begin
if(!rst_n) begin
slow_ack <= 1'b0;
end else if (slow_req[1] & (~slow_req[2])) begin
slow_ack <= 1'b1;
end else begin
slow_ack <= (slow_req[2] & (~slow_req[1])) ? 1'b0 : slow_ack;
end
end
assign dataout = (~slow_req[2]) & (slow_req[1]);
//
endmodule
