题解 | #可置位计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);

reg    [3:0]    num_reg;

always@(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin 
       num_reg <= 4'd0; 
    end
    else    if(set)begin 
       num_reg <= set_num; 
    end
    else    begin 
       num_reg <= num_reg + 1'b1; 
    end
end

always@(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin 
       zero <= 1'd0; 
    end
    else    if(num_reg == 4'b0)begin 
       zero <= 1'b1; 
    end
    else    begin 
       zero <= 1'b0;
    end
end
               
always@(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin
        number <= 4'd0;
    end
    else    begin 
       number <= num_reg; 
    end
end
         
endmodule