题解 | #自动贩售机1#
自动贩售机1
http://www.nowcoder.com/practice/dcf59e6c51f6489093495acb1bc34dd8
````timescale 1ns/1ns
module seller1(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire d3 ,
output reg out1,
output reg [1:0]out2
);
//*************code***********//
localparam IDLE = 0,
HALF = 1,
ONE = 2,
ONE_HALF = 3,
TWO = 4,
TWO_HALF = 5,
THREE =6;
reg[2:0] curr_state,next_state;
always @(posedge clk or negedge rst)begin
if(~rst)
curr_state <= IDLE;
else
curr_state <= next_state;
end
always @(*)begin
case(curr_state)
IDLE :begin
next_state =d1? HALF:
d2? ONE:
d3? TWO:
next_state;
end
HALF :begin
next_state =d1? ONE:
d2? ONE_HALF:
d3? TWO_HALF:
next_state;
end
ONE :begin
next_state =d1? ONE_HALF:
d2? TWO:
d3? THREE:
next_state;
end
ONE_HALF :next_state =IDLE;
TWO :next_state =IDLE;
TWO_HALF :next_state =IDLE;
THREE :next_state =IDLE;
default :next_state =IDLE;
endcase
end
always @(posedge clk or negedge rst)begin
if(~rst)begin
out1 <= 0;
out2 <= 0;
end else begin
case(next_state)
ONE_HALF:begin
out1 <= 1'b1; out2<=0;
end
TWO :begin
out1 <= 1'b1; out2<=1;
end
TWO_HALF:begin
out1 <= 1'b1; out2<=2;
end
THREE :begin
out1 <= 1'b1; out2<=3;
end
default :begin
out1 <= 1'b0; out2<=0;
end
endcase
end
end
//*************code***********//
endmodule
