题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2( input wire clk , input wire rst , input wire data , output reg flag ); //**code// reg [3:0] temp; always @(posedge clk or negedge rst) if(!rst)begin temp<=4'd0; end else begin temp<={temp[2:0],data}; end

always @(posedge clk or negedge rst)
    if(!rst)begin
        flag<=1'd0;
    end else if(temp==4'b1011)begin
        flag<=1'd1;
    end else begin
        flag<=1'd0;
    end

//**code// endmodule